The present invention relates generally to semiconductor devices, and more particularly to data compression and/or parallel data testing of the memory cells in a semiconductor memory device.
Semiconductor memory devices typically include a large number of memory cells, each of which can store one or more bits of data. The memory cells are arranged in an array, having a number of rows and columns. Memory cells within the same row are commonly coupled to a word line, and memory cells within the same column are commonly coupled to a bit line. The memory cells within an array are accessed according to the various memory device operations. Such operations include read operations (common to nearly all memory devices), write operations (common to volatile memory devices), and program and erase operations (common to many nonvolatile memory devices). To access memory cells, an external memory address is applied, which activates a word line. When activated, row decoder circuits couple the data stored within the memory cells to the bit lines of the array. The memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits and/or program/erase circuits.
There are instances in which the user or manufacturer may wish to perform a high speed test of the data stored in the memory cells of the semiconductor memory device. For example, in the course of fabricating a semiconductor memory device, manufacturing defects can give rise to nonfunctional memory cells within an array. In order to quickly test the functionality of the memory cells, many semiconductor memories may have a feature known as parallel testing. In a normal read or write operation, the input/output (DQ) pins will carry data representative of a single particular addressed memory cell in the semiconductor memory device. However, in a parallel test write operation, a single write operation may simultaneously write the data applied to a single DQ pin into a large number of memory cells. Conversely, in a parallel test read operation, a single read operation may compare data from a large number of memory cells and if the data is all of the same logic level, a xe2x80x9cmatchxe2x80x9d logic level will be applied to the DQ pin. If any of the number of memory cells has a data level different than the other memory cells being compared then a xe2x80x9cmis-matchxe2x80x9d logic level will be applied to the DQ pin.
The ability to test multiple memory cells in one read operation enables the manufacturer or user to reduce test time. Reducing test time saves money because the test throughput will be increased and a piece of test equipment will be able to test more memory devices in the same amount of time. This allows the manufacture to purchase fewer pieces of test equipment.
A user may wish to use the parallel test capabilities to test the semiconductor memory device in his unique system environment. For example, the system environment may have an impact on the xe2x80x9csoftxe2x80x9d errors that occur in a memory device as every system may operate at a unique temperature, voltage, signal noise conditions, or even exposure to alpha particles or gamma rays. The user may use parallel test write cycles to write all logic ones into all of the semiconductor memory cells, then do a xe2x80x9cpausexe2x80x9d by not executing any cycles over a period of time known as the xe2x80x9cpausexe2x80x9d time. Then the user will perform the parallel test read cycles to determine if any xe2x80x9csoftxe2x80x9d errors have been induced in the semiconductor memory device by the system environment. The user takes advantage of the parallel testing capabilities to reduce the total test time required, thus, increasing test throughput.
Dynamic Random Access Memories (DRAMs) generally come in non-synchronous (DRAM) and synchronous (SDRAM) types. A non-synchronous DRAM will perform read and write cycles based on a Row Address Strobe (RAS) signal, Column Address Strobe (CAS) signal, and Write (W) signal. A SDRAM has an added Clock (CLK) signal that operates synchronously with the system and allows much faster data throughput than a non-synchronous DRAM. The faster data throughput (decreased read/write cycle time) means that data compression or comparison must be performed at faster speeds during the parallel test cycles in order to keep the same tight timing requirements in the test mode as is used in normal modes of operation.
Chip (die) size is an important aspect of the semiconductor memory business. The smaller the chip, the more chips per silicon wafer can be manufactured. This decreases total cost per chip because the processing cost of each wafer is constant regardless of the number of chips contained on the wafer. Today, many semiconductor memory devices are of a wide word type. For example, there may be 16, 32, 64 or even more output pins (DQs) per chip. On the chip itself, the portion of the semiconductor memory array that corresponds to each DQ will be located as close as possible to the DQ bond pad. This allows the data lines that transport data from the bond pad to the array portion to be as short as possible. This improves speed due to lower capacitive and resistive effects and decreases chip size because there are not a large number of data lines running the length of the memory chip, thus taking up valuable space. However, in order to perform parallel test operations, a large number of data bits must be brought to the compare circuitry and the results of the comparison must be placed on a desired output pin (DQ). One method of bringing the large number of data bits together to be compared and/or compressed is to route the data lines on the chip to the location in which the compression/comparison circuit is located. This will take up valuable signal routing channels that are typically needed to route address and control signals to critical timing circuits. Additionally, this has the adverse effect of increasing data line resistance and capacitance and increasing the chip size because each data line will take up more area.
It would be desirable to provide data compression/comparison on a semiconductor memory device while occupying few signal routing channels and thus have less of an effect on chip size. It is also desirable to provide a method of data compression/comparison on the semiconductor memory device that can operate at high speeds, as may be needed in a synchronous memory as for example a SDRAM.
According to the present invention, a semiconductor memory device includes a parallel data test scheme. The semiconductor memory includes an array that is partitioned into array portions with each array portion further divided into sub-arrays and banks. Each array portion provides data bits to a data compression circuit. The data compression circuit includes data compare sections and ripple sections. The data compare sections include data compare circuits that compare the data bits provided by each array portion and provide a compare output to the ripple sections. The compare output has a true logic level, a false logic level, and an error logic level. The ripple sections are coupled together in series and provide a global data compare output. The ripple sections include ripple circuits that receive the compare output and ripple outputs. The ripple outputs have a true logic level, a false logic level, and an error logic level. A multiplexer selects between a data bit and a global data compare output, that is provided from the last of the chain of ripple circuits coupled together in series, to provide either a data output or a data a comparison output to an output pin.
According to one aspect of the invention, the compare circuit has a true compare portion and a false compare portion providing a true output and a false output having the same logic level if the data compare does not produce an error.
According to another aspect of the invention, the ripple outputs are carried by conductors hat have a length substantially smaller than the length of the semiconductor memory die.